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quad channel, 128-/256-position, i 2 c, nonvolatile digital potentiometer data sheet ad5123 / ad5143 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2012C2013 analog devices, inc. all rights reserved. technical support www.analog.com features 10 k and 100 k resistance options resistor tolerance: 8% maximum wiper current: 6 ma low temperature coefficient: 35 ppm/c wide bandwidth: 3 mhz fast start-up time < 75 s linear gain setting mode single- and dual-supply operation wide operating temperature: ?40c to +125c 3 mm 3 mm package 4 kv esd protection applications portable electronics level adjustment lcd panel brightness and contrast controls programmable filters, delays, and time constants programmable power supplies functional block diagram v dd v ss gnd 7/8 serial interface power-on reset rdac1 input register 1 rdac2 input register 2 rdac3 input register 3 rdac4 input register 4 eeprom memory a 1 w 1 b 1 a 2 w 2 b 2 w 3 b 3 w 4 b 4 ad5123/ad5143 scl sda a ddr 10878-001 figure 1. general description the ad5123 / ad5143 potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of 8% and up to 6 ma current density in the ax, bx, and wx pins. the low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. the linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through the r aw and r wb string resistors, allowing very accurate resistor matching. the high bandwidth and low total harmonic distortion (thd) ensure optimal performance for ac signals, making the devices suitable for filter design. the low wiper resistance of only 40 at the ends of the resistor array allows for pin-to-pin connection. the wiper values can be set through an i 2 c-compatible digital interface that is also used to read back the wiper register and eeprom contents. the ad5123/ ad5143 are available in a compact, 16-lead, 3 mm 3 mm lfcsp. the parts are guaranteed to operate over the extended industrial temperature range of ?40c to +125c. table 1. family models model channel position interface package ad5123 1 quad 128 i 2 c lfcsp ad5124 quad 128 spi/i 2 c lfcsp ad5124 quad 128 spi tssop ad5143 quad 256 i 2 c lfcsp ad5144 quad 256 spi/i 2 c lfcsp ad5144 quad 256 spi tssop ad5144a quad 256 i 2 c tssop ad5122 dual 128 spi lfcsp/tssop ad5122a dual 128 i 2 c lfcsp/tssop ad5142 dual 256 spi lfcsp/tssop ad5142a dual 256 i 2 c lfcsp/tssop ad5121 single 128 spi/i 2 c lfcsp ad5141 single 256 spi/i 2 c lfcsp 1 two potentiometers and two rheostats.
ad5123/a d5143 data sheet rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ad5123 .......................................... 3 electrical characteristics ad5143 .......................................... 6 inte rface timing specifications .................................................. 9 shift register and timing diagrams ....................................... 10 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 13 test circuits ..................................................................................... 18 theory of operation ...................................................................... 19 rdac register and eeprom .................................................. 19 input shift register .................................................................... 19 i 2 c seria l data interface ............................................................ 19 i 2 c address .................................................................................. 19 advanced control modes ......................................................... 21 eep rom or rdac register protection ................................. 22 rdac architecture .................................................................... 25 programming the variable resistor ......................................... 25 programming the potentiometer divider ............................... 26 terminal voltage operating range ......................................... 26 power - up sequence ................................................................... 26 layout and power supply biasing ............................................ 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 3 / 13 rev. 0 to rev. a changes to features section ............................................................ 1 10/ 12 rev ision 0: initial version
data sheet ad5123/ad5143 rev. a | page 3 of 28 specifications electrical character istics ad512 3 v dd = 2.3 v to 5.5 v, v ss = 0 v; v dd = 2.25 v to 2.75 v, v ss = ?2.25 v to ?2.75 v; ? 40c < t a < +125c, unless otherwise noted. table 2 . parameter symbol test conditions/comments min typ 1 max unit dc characteristics rheostat mode (all rdacs) resolution n 7 bits resistor integra l nonlinearity 2 r - inl r ab = 10 k ? v dd 2.7 v ? 1 0. 1 + 1 lsb v dd < 2.7 v ? 2.5 1 + 2.5 lsb r ab = 100 k ? v dd 2.7 v ? 0.5 0.1 + 0.5 lsb v dd < 2.7 v ? 1 0. 25 + 1 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0. 1 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance 3 r w code = zero sc ale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom scale o r top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? nominal resistance match r ab1 /r ab2 code = 0xff ? 1 0.2 +1 % dc characteristics potentiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 0.5 0. 1 + 0.5 lsb r ab = 100 k ? ? 0. 25 0.1 +0. 25 lsb differential nonlinearity 4 dnl ? 0. 25 0. 1 +0. 25 lsb full - scale error v wfse r ab = 10 k ? ? 1 .5 ? 0.1 lsb r ab = 100 k ? ? 0.5 0. 1 + 0.5 lsb zero - scale error v wzse r ab = 10 k ? 1 1.5 lsb r ab = 100 k ? 0. 25 0.5 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c
ad5123/a d5143 data sheet rev. a | page 4 of 28 parameter symbol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 10 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na digital inputs input logic 3 high v inh 0.7 v dd v low v inl 0.2 v dd v input hysteresis 3 v hyst 0.1 v dd v input current 3 i in 1 a input capacitance 3 c in 5 p f digital outputs output high voltage 3 v oh r pull - up = 2.2 k ? to v dd v dd v output low voltage 3 v ol i sink = 3 ma 0.4 v i sink = 6 ma 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply po wer range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd v dd = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v dd or v il = gnd ? 5.5 ? 0.7 a ee prom store current 3 , 6 i dd_ee prom _store v ih = v dd or v il = gnd 2 ma ee prom read current 3 , 7 i dd_ee prom _read v ih = v dd or v il = gnd 320 a power dissipation 8 p dis s v ih = v dd or v il = gnd 3.5 w power supply rejection ratio psr r ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db
data sheet ad5123/ad5143 rev. a | page 5 of 28 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandwidth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb erro r band r ab = 10 k ? 2 s r ab = 100 k ? 12 s crosstalk (c w1 /c w2 ) c t r ab = 10 k ? 10 nv - sec r ab = 100 k ? 25 nv - sec analog crosstalk c ta ? 90 db endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent average readings a t 25c, v dd = 5 v, and v ss = 0 v. 2 resistor integral nonlinearity (r - inl) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal bet ween successive tap positions. the maximum wiper current is limited to (0.7 v dd )/r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider simil ar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 r esistor t erminal a, r esistor t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation enables ground referenced bipolar signal adjustment . 6 different from operating current; supply current for eeprom program lasts approximately 30 ms . 7 different from operating current; supply current for eeprom read last s approximately 20 s . 8 p diss is calculated from (i dd v dd ) . 9 all dynamic characteristics use v dd / v ss = 2.5 v . 10 endurance is qualified to 100,000 cycles per jedec standard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equivale nt at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates with junction temperature in the flash/ee memory.
ad5123/a d5143 data sheet rev. a | page 6 of 28 electrical character istics ad5143 v dd = 2.3 v to 5.5 v, v ss = 0 v; v dd = 2.25 v to 2.75 v, v ss = ?2. 25 v to ?2.75 v; ?40c < t a < +125c, unless otherwise noted. table 3 . parameter symbol test conditions/comments min typ 1 max unit dc characteristics rheostat mode (all rdacs) resolution n 8 bits resistor integral nonlinearity 2 r - inl r ab = 10 k ? v dd 2.7 v ? 2 0.2 +2 lsb v dd < 2.7 v ? 5 1.5 +5 lsb r ab = 100 k ? v dd 2.7 v ? 1 0.1 +1 lsb v dd < 2.7 v ? 2 0.5 +2 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0.2 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance te mperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance 3 r w code = zero scale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom s cale or top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? nominal resistance match r ab1 /r ab2 code = 0xff ? 1 0.2 +1 % dc characteristics potentiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 1 0.2 +1 lsb r ab = 100 k ? ? 0.5 0.1 +0.5 lsb differential nonlinearity 4 dnl ? 0.5 0.2 +0.5 lsb full - scale error v wfse r ab = 10 k ? ? 2.5 ? 0.1 lsb r ab = 100 k ? ? 1 0.2 +1 lsb zero - scale error v wzse r ab = 10 k ? 1.2 3 lsb r ab = 100 k ? 0.5 1 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c
data sheet ad5123/ad5143 rev. a | page 7 of 28 parameter symbol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 10 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na digital inputs input logic 3 high v inh 0.7 v dd v low v inl 0.2 v dd v input hysteresis 3 v hyst 0.1 v dd v input curr ent 3 i in 1 a input capacitance 3 c in 5 pf digital outputs output high voltage 3 v oh r pull - up = 2.2 k ? to v dd v dd v output low voltage 3 v ol i sink = 3 ma 0.4 v i sink = 6 ma 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply power range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd v dd = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v dd or v il = gnd ? 5.5 ? 0.7 a ee prom st ore current 3 , 6 i dd_ee prom _store v ih = v dd or v il = gnd 2 ma ee prom read current 3 , 7 i dd_ee prom _read v ih = v dd or v il = gnd 320 a power dissipation 8 p diss v ih = v dd or v il = gnd 3.5 w power supply rejection ratio psr r ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db
ad5123/a d5143 data sheet rev. a | page 8 of 28 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandwidth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb erro r band r ab = 10 k ? 2 s r ab = 100 k ? 12 s crosstalk (c w1 /c w2 ) c t r ab = 10 k ? 10 nv - sec r ab = 100 k ? 25 nv - sec analog crosstalk c ta ? 90 db endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent average readings at 25c, v dd = 5 v , and v ss = 0 v. 2 resistor integral nonlinearity (r - inl) error is the deviation from an ideal value measured between the maximum resistance and the minim um resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is limited to (0.7 v dd )/r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 r esistor t erminal a, r esisto r t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation enables ground referenced bipolar signal adjustment . 6 different from operating current; supply current for eeprom program lasts approxi mately 30 ms . 7 different from operating current; supply current for eeprom read lasts approximately 20 s . 8 p diss is calculated from (i dd v dd ) . 9 all dynamic characteristics use v dd / v ss = 2.5 v . 10 endurance is qualified to 100,000 cycles per jedec sta ndard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates with junction temperature in the flash/ee memory.
data sheet ad5123/ad5143 rev. a | page 9 of 28 interface timing spe cifications v dd = 2.3 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 4 . i 2 c interface parameter 1 test conditions/comments min typ max unit description f scl 2 standard mode 100 khz serial clock frequency fast mode 400 khz t 1 standard mode 4.0 s scl high time , t high fast mode 0.6 s t 2 standard mode 4.7 s scl low time , t low fast mode 1.3 s t 3 standard mode 250 ns d ata setup t ime , t su; dat fast mode 100 ns t 4 standard mode 0 3.45 s d ata hold time , t hd; dat fast mode 0 0.9 s t 5 standard mode 4.7 s s etup time for a repeated start condition , t su; sta fast mode 0.6 s t 6 standard mode 4 s h old time (repeated) for a start condition , t hd; sta fast mode 0.6 s t 7 standard mode 4.7 s b us free time between a stop and a start condition , t buf fast mode 1.3 s t 8 standard mode 4 s s etup time for a stop condition , t su; sto fast mode 0.6 s t 9 standard mode 1000 ns r ise time of sda signal , t rda fast mode 20 + 0.1 c l 300 ns t 10 standard mode 300 ns f all time of sda signal , t fda fast mode 20 + 0.1 c l 300 ns t 11 standard mode 100 0 ns r ise time of scl signal , t rcl fast mode 20 + 0.1 c l 300 ns t 11a standard mode 1000 ns r ise time of scl signal after a repeated start condition and after an acknowledge bit , t rcl1 (not shown in figur e 3 ) fast mode 20 + 0.1 c l 300 ns t 12 standard mode 300 ns f all time of scl signal , t fcl fast mode 20 + 0.1 c l 300 ns t sp 3 fast mode 0 50 ns pulse width of suppressed spike (not shown in figu re 3 ) t eeprom_program 4 15 50 ms memory program time (not shown in figure 3 ) t eeprom_readback 7 30 s memory readback time (not shown in figure 3 ) t power_up 5 75 s power - on eeprom restore time ( not shown in figure 3 ) t reset 30 s reset eeprom restore time (not shown in figure 3 ) 1 maximum bus capacitance is limited to 400 pf. 2 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate ; however, it has a negative effect on the emc behavior of the part. 3 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns for fast mode. 4 ee prom program time depends on the temperature and ee prom write cycles. higher timing is expected at lower temperature s and higher write cycles. 5 maximum time after v dd ? v ss is equal to 2.3 v.
ad5123/ad5143 data sheet rev. a | page 10 of 28 shift register and timing diagrams data bits db8 db15 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 addr ess bits a0 a1 a2 c2 c1 c0 a3 c3 control bits db7 10878-002 figure 2. input shift register contents t 7 t 6 t 2 t 4 t 11 t 12 t 6 t 5 t 10 t 1 scl sd a ps s p t 3 t 8 t 9 10878-003 figure 3. i 2 c serial interface timing diagram (typical write sequence)
data sheet ad5123/ad5143 rev. a | page 11 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5 . parameter rating v dd to gnd ? 0.3 v to +7.0 v v ss to gnd + 0.3 v to ? 7.0 v v dd to v ss 7 v v a , v w , v b to gnd v ss ? 0.3 v, v dd + 0.3 v or +7.0 v (whichever is less) i a , i w , i b pulsed 1 frequency > 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 frequency 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 digital inputs ? 0.3 v to v dd + 0.3 v or +7 v (whichever is less) operating temperature range, t a 3 ? 40 c to +125c maximum junction temperature, t j m ax imum 150c storage temperature range ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja esd 4 4 kv ficdm 1.5 kv 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and ma ximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 d = p ulse duty factor. 3 includes programming of eeprom memory. 4 human body model (hbm) classification. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated i n the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by the jedec jesd51 standard, and the value is dependent on the test board and test environment. table 6 . thermal resistance package type ja jc unit 16- lead lfcsp 89.5 1 3 c/w 1 jedec 2s2p test board, still air (0 m/s ec airflow). esd caution
ad5123/ad5143 data sheet rev. a | page 12 of 28 pin configuration an d functi on descriptions notes 1. internally connect the exposed pad to v ss . ad5123/ ad5143 top view (not to scale) pin 1 indic a t or 1 a1 2 w1 3 b1 4 w3 1 1 b4 12 v dd 10 w4 9 b2 addr gnd sd a sc l 5 b3 6 v ss 7 a2 8 w2 15 16 14 13 10878-004 figure 4 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 a1 terminal a of rdac1. v ss v a v dd . 2 w1 wiper t erminal of rdac1. v ss v w v dd . 3 b1 terminal b of rdac1. v ss v b v dd . 4 w3 wiper t erminal of rdac3. v ss v w v dd . 5 b3 terminal b of rdac3. v ss v b v dd . 6 v ss negative power supply. decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 7 a2 terminal a of rdac2 . v ss v a v dd . 8 w2 wiper t erminal of rdac2. v ss v w v dd . 9 b2 terminal b of rdac2. v ss v b v dd . 10 w4 wiper t erminal of rdac4. v ss v w v dd . 11 b4 terminal b of rdac4. v ss v b v dd . 12 v dd positive power supply. decouple t his pin with 0. 1 f ceramic capacitors and 10 f capacitors . 13 scl serial clock line. data is clocked in at the logic low transition. 14 sda serial data input/output . 15 addr programmable a ddress for multiple package decoding. 16 gnd ground pin, logic ground refere nce. epad internally connect the exposed paddle to v ss .
data sheet ad5123/ad5143 rev. a | page 13 of 28 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 100 200 r-inl (lsb) code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10878-005 figure 5. r - inl vs. code ( ad5143 ) r-inl (lsb) code (decimal) ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 50 100 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10878-006 figure 6. r - inl vs. code ( ad5123 ) 0 100 200 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 in l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, + 2 5 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 2 5 c 100k ?, + 12 5 c 10878-007 figure 7. inl vs. code ( ad5143 ) ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0 100 200 r-dn l (lsb) code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10878-008 figure 8. r - dnl vs . code ( ad5143 ) code (decimal) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 50 100 r-dn l (lsb) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10878-009 figure 9. r - dnl vs. code ( ad5123 ) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 dn l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c 10878-010 0 100 200 figure 10 . dnl vs. code ( ad5143 )
ad5123/ad5143 data sheet rev. a | page 14 of 28 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 50 100 in l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, + 2 5 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 2 5 c 100k ?, + 12 5 c 10878-0 1 1 figure 11 . inl vs. code ( ad5123 ) ?50 0 50 100 150 200 250 300 350 400 450 potentiometer mode temperature coefficient (ppm/c) 100k ? 10k ? 10878-012 ad 512 3 ad5143 code (decimal) 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 figure 12 . potentiometer mode temp eratu re c o efficient (( v w /v w )/ t 10 6 ) vs. code 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 curr en t (n a ) t emper a t ur e ( c ) 1087 8-013 i dd , v dd = 2.3v i dd , v dd = 3.3v i dd , v dd = 5v ?4 0 1 0 6 0 1 25 1 10 v s s = g n d figure 13 . supply current vs. temperature ?0.14 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0 50 100 dn l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c 10878-014 figure 14 . dnl vs. code ( ad5123 ) ?5 0 0 5 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 rhe o s t a t m o d e t empe rat ure c o e ff i c i e n t ( pp m / c ) 10 k? 100 k? 10878-015 ad 512 2a ad5142a code (decimal) 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 figure 15 . rheostat mode temperature coefficient (( r wb /r wb )/ t 10 6 ) vs. code 0 200 400 600 800 1000 1200 0 1 2 3 4 5 i dd current ( a) input voltage (v) v dd = 2.3v v dd = 3.3v v dd = 5v v dd = 5.5v 10878-016 figure 16 . i dd current vs. digital input voltage
data sheet ad5123/ad5143 rev. a | page 15 of 28 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) ad5143 (ad5123) 0x80 (0x40) 0x40 (0x20) 0x20 (0x10) 0x10 (0x08) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 10878-017 figure 17 . 10 k? gain vs. frequency and code ?10 0 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 2 0 20 0 2 k 20 k 200 k t hd + n ( d b ) f r e q u e n c y ( h z) 10 k ? 100 k ? v d d / v s s = 2 . 5 v v a = 1 v rm s v b = g n d c o d e = ha lf s ca l e n oi se f i lt e r = 22k h z 10878-018 figure 18 . total harmonic distortion plus noise (thd + n) vs. frequency ?100 ?80 ?60 ?40 ?20 0 20 10 100 1k 10k 100k 1m 10m phase (degrees) frequenc y (hz) quarter scale midscale full-scale v dd /v ss = 2.5v r ab = 10k 10878-019 figure 19 . normalized phase flatness vs. frequency, r ab = 10 k? ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 gain (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m 0x80 (0x40) 0x40 (0x20) 0x20 (0x10) 0x10 (0x08) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 ad5143 (ad5123) 10878-020 figure 20 . 100 k? gain vs. frequency and code 10 k ? 100 k ? ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 0 . 00 1 0 . 0 1 0 . 1 1 t hd + n ( d b ) vo l t a g e (v rms ) v dd /v ss = 2 . 5 v f in = 1k h z c o d e = ha lf sca l e n oi se f i lter = 2 2 k h z 10878-021 figure 21 . total harmonic distortion plus noise (thd + n) vs. amplitude ?80 ?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 100 1k 10k 100k 1m phase (degrees) frequenc y (hz) quarter scale midscale full-scale v dd /v ss = 2.5v r ab = 100k 10878-022 figure 22 . normalized phase flatness vs. frequency, r ab = 100 k?
ad5123/ad5143 data sheet rev. a | page 16 of 28 0 100 200 300 400 500 600 0 1 2 3 4 5 wiper on resis t ance ( ) volt age (v) 100k, v dd = 2.3v 100k, v dd = 2.7v 100k, v dd = 3v 100k, v dd = 3.6v 100k, v dd = 5v 100k, v dd = 5.5v 10k, v dd = 2.3v 10k, v dd = 2.7v 10k, v dd = 3v 10k, v dd = 3.6v 10k, v dd = 5v 10k, v dd = 5.5v 10878-023 figure 23 . incremental wiper on resistance vs. positive power supply ( v dd ) 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 0 10 20 30 40 50 60 bandwidth (mhz) code (decimal) ad5143 ad5123 10k ? + 0pf 10k ? + 75pf 10k ? + 150pf 10k ? + 250pf 100k ? + 0pf 100k ? + 75pf 100k ? + 150pf 100k ? + 250pf 10878-024 figure 24 . maximum bandwidth vs. code and net capacitance ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5 10 15 rel a tive vo lt age (v) time ( s) 0x80 to 0x7f 100k 0x80 to 0x7f 10k 10878-025 figure 25 . maximum transition glitch 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 0 0 . 000 5 0 . 001 0 0 . 001 5 0 . 002 0 0 . 002 5 ?40 0 ?50 0 ?60 0 ?30 0 ?20 0 ?10 0 0 10 0 20 0 30 0 40 0 50 0 60 0 cu m u l a ti ve p r obab i l i t y p r obab i l i t y d e n s i t y r esi st o r dr if t (ppm ) 10878-026 figure 26 . resistor life ti me drift ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) 10k, rdac1 100k, rdac1 10878-027 v d d = 5 v 10% a c v s s = g nd , v a = 4 v , v b = g n d c o d e = m i d s ca l e figure 27 . power supply rejection ratio (psrr) vs. frequency ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0 500 1000 1500 2000 rel a tive vo lt age (v) time (ns) 10878-028 figure 28 . digital feedthrough
data sheet ad5123/ad5143 rev. a | page 17 of 28 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) 10k 100k 10878-029 s hu t d o w n m o d e e nab l ed figure 29 . shutdown isolation vs. frequency 0 1 2 3 4 5 6 7 0 50 100 150 200 250 0 25 50 75 100 125 ad5123 theoretica l i max (ma) ad5143 100k? 10k? code (decimal) 10878-030 figure 30 . theoretical maximum current vs. code
ad5123/ad5143 data sheet rev. a | page 18 of 28 test circuits figure 31 to figure 35 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 10878-031 figure 31 . resistor integral nonlinearity error (rheostat operation; r - inl, r - dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n 10878-032 figure 32 . potentiometer divider nonlinearity error (inl, dnl) 10878-033 a w b du t i w = v d d / r n o m i n a l v m s 1 v w r w = v m s 1 / i w nc = n o c o nn e c t figure 33 . wiper resistance a w b v ms v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) ~ v a v dd v ms % v dd % pss ( %/% ) = v+ 10878-034 figure 34 . power supply sensitivity and power supply rejection ratio (pss, psrr) + ? dut code = 0x00 0.1v v ss t o v dd r sw = 0.1v i sw i sw w b a = nc 10878-035 figure 35 . incremental on resistance
data sheet ad5123/ad5143 rev. a | page 19 of 28 theory of operation the ad5123 / ad5143 digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of v ss < v term < v dd . the resistor w iper position is determined by the rdac register contents. the r dac register acts as a scratchpad register that allows unlimited changes of resistance settings. a secondary register (the input register ) can be used to preload the rdac register data. the rd ac register can be programmed with any position setting using the i 2 c interface (depending on the model). when a desirable wiper position is found, this value can be stored in the eeprom memory. thereafter, the wiper position is always restored to that pos ition for subsequent power - up s . the storing of eeprom data takes approximately 1 5 ms; during this time, the device is locked and does not acknowledge any new command , preventing any changes from taking place. rdac r egister and eeprom the rdac register dire ctly controls the position of the digital potentiometer wiper. for example, when the rdac register is loaded with 0x80 ( ad5143 , 256 taps), the wiper is connected to half scale of the variable resis tor. the rdac register is a standard logic register; there is no restriction on the number of changes allowed . it is possible to both write to and read from the rdac register using the digital interface ( see table 9 ) . the content s of the rdac register can be stored to the eeprom using c ommand 9 ( see table 9 ) . thereafter , the rdac register always set s at that position for any future on - off - on power supply sequence. it is possible to read ba ck data saved into the eeprom with c ommand 3 ( see table 9 ) . alternatively, the eeprom can be writ t e n to independently using c ommand 1 1 ( see table 15) . input shift register for the ad5123 / ad5143 , the input shift register is 16 bits wide, as shown in figure 2 . the 16 - bit word consists of four control bits, followed by four address bits and by eight data bits . i f the ad5143 rdac or ee prom registers are read from or written to , the lowe st data bit (bit 0) is ignored. data is load ed msb first (bit 15). the four control bits determine the function of the software command , as listed in table 9 and table 15. i 2 c serial data interf ace the ad5123 / ad5143 ha s 2 - wire , i 2 c - compatible serial interfaces . these devices can be connected to an i 2 c bus as a slave device, under the control of a master device . see figure 3 for a timing diagram of a typical write sequence. the ad5123 / ad5143 support s standard (100 khz) and fast (400 khz) d ata transfer modes. support is not provided for 10- bit addressing and general call addressing. the 2 - wire serial bus protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition, which is when a high - to - low transiti on on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7 - bit slave address and a n r/ w bit. the slave device corresponding to the transmitted address responds by pulling sda low during th e ninth clock pulse (this is call ed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. if the r/ w bit is set high, the master reads from the slave device. however, if the r/ w bit is set low, the master writes to the slave device. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). th e transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read from or written to , a stop condition is established. in write mode, the master pulls the sda line high during the ten th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the ten th clock pulse, and then high again during the ten th clock pulse to establish a stop condition. i 2 c address the facility to make hardwired changes to addr allows the user to incorporate up to three of these devices on one bus as outlined in tab le 8 . table 8 . i 2 c address selection addr pin 7 - bit i 2 c device address v dd 0101000 no connect 1 0101010 gnd 0101011 1 n ot available in bipolar mode ( v ss < 0 v ) .
ad5123/ad5143 data sheet rev. a | page 20 of 28 table 9 . reduced commands operation t ruth table command number co ntrol bits [db15:db12] address bits [db11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing 1 0 0 0 1 0 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 writ e contents of serial register data to rdac 2 0 0 1 0 0 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 0 0 a1 a0 x x x x x x d1 d0 read back contents d1 d0 d ata 0 1 e eprom 1 1 rdac 9 0 1 1 1 0 0 a1 a0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 0 0 a1 a0 x x x x x x x 0 copy eeprom into rdac 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 a3 0 a1 a0 x x x x x x x d0 softw are shutdown d0 condition 0 normal mode 1 shutdown mode 1 x = dont care. table 10. reduced address bits table a3 a 2 a1 a 0 channel stored channel memory 1 x 1 x 1 x 1 all chann els not applicable 0 0 0 0 rdac1 rdac1 0 0 0 1 rdac2 rdac2 0 0 1 0 rdac3 rdac3 0 0 1 1 rdac4 rdac4 1 x = dont care.
data sheet ad5123/ad5143 rev. a | page 21 of 28 advanced control mod es the ad5123 / ad5143 digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices ( see table 15 and table 17 ) . key programming features include the following: ? input register ? linea r gain setting mode ? low wiper resistance feature ? linea r i ncrement and decrement instructions ? 6 db increment and decrement instructions ? burst m ode (i 2 c onl y) ? reset ? shutdown mode input r egister the ad5123 / ad5143 include one input register per rdac register. these registers allow preloading of the value for the associate d rdac register. the se register s can be written to using command 2 and read back using command 3 (see table 15 ). this feature allows a synchronous and asynchronous update of one or all of the rdac regis ters at the same time. the transfer from the input register to the rdac register is done synchronously by c ommand 8 (see table 15) . if new data is loaded in a n rdac register , th is rdac register automatically overwrites the associa te d input register. linea r gain setting m ode the patented architecture of the ad5123 / ad5143 allows the independent control of each string resistor, r aw , and r wb . to enable linear gain setting mode , use command 16 (see table 15 ) to set bit d2 of the control register (see table 17) . this mode of operation can control the poten tiometer as two independent rheostats connected at a single point, w terminal, as opposed to potentiometer mode where each resistor is complementary, r aw = r ab ? r wb . this mode enables a second input and a n rdac register per channel, as shown in table 16 ; however, the actual rdac content s remain unchanged. the same operations are valid for potentiometer and linea r setting gain mode s. the part s restore in potentiometer mode after a reset or power - up. low wiper resistance f ea ture the ad5123 / ad5143 include two commands to reduce the wiper resistance between the terminals when the device s achieve full scale or ze ro scale. these extra positions are called bottom scale, bs, and top scale, ts. the resistance between terminal a and terminal w at top scale is specified as r ts . similarly, the bottom scale resistance between terminal b and terminal w is specifi ed as r bs . the contents of the rdac registers are unchanged by entering in these positions. there are three ways to exit from top scale and bottom scale: by using command 12 or command 13 (see table 15) ; by loading new data in a n rdac regis ter, which includes increment/decrement operations ; or by entering shutdown mode, command 15 (see table 15) . table 11 and table 12 show the truth tables for the t op scale position and the bottom scale position, respectively, when the potentiometer or linear gain setting mode is enabled. table 11. top scale truth table linear gain setting mode potentiometer mode r aw r wb r aw r wb r ab r ab r ts r ab table 12. bottom scale truth table linear gain setting mode potentiometer mode r aw r wb r aw r wb r ts r bs r ab r bs linear increment and decrement instructions the increment and decrement commands ( command 4 and command 5 in table 15 ) are useful for linear step adjustment applications. these commands simplify microcontroller software coding by allowing the controller to send an increment or decrement command to the device. the adjustment can be individu al or in a ganged potentiometer arrangement , where all wiper positions are changed at the same time. for an increment command, executing command 4 automatically moves the wiper to the next resistance rdac position . this command can be executed in a single channel or multiple channels .
ad5123/ad5143 data sheet rev. a | page 22 of 28 6 db increment and decrement instructions two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer ar rangement where all rdac register positions are changed simultaneously . the +6 db increment is activated by command 6, and the ? 6 db decrement is activated by command 7 ( see table 15) . for example, starting with the zero - scale pos ition and executing command 6 ten times moves the wiper in 6 db steps to the full - scale position . when the wiper position is near the maximum setting, the last 6 db increment instruction cause s the wiper to go to the full - scale position ( see table 13) . incr ementing the wiper position by + 6 db essentially doubles the rdac register value, whereas decrementing the wiper position by ? 6 db halves the register value . internally, the ad5123 / ad5143 use shift registers to shift the bits left and right to achieve a 6 db inc rement or decrement. these functions are useful for various audio/video level adjustments, especially for white led brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. table 13 . detailed left shift and right shift functions for the 6 db step increment and decrement left shift (+6 db/step) right shift ( ? 6 db/step) 0000 0000 1111 1111 0000 0001 0111 1111 0000 0010 0011 1111 0000 0100 0001 1111 0000 1000 0000 1111 0001 0000 0000 0111 0010 0000 0000 0011 0100 0000 0000 0001 1000 0000 0000 0000 1111 1111 0000 0000 burst mode by enabling the bur st mode, multiple data bytes can be sent to the part consecutively. after the command byte, the part interprets the consecutive bytes as data bytes for the command. a new command can be sent by generating a repeat start or by a stop and start condition. th e burst mode is activ ated by setting bit d3 of the control register (see table 17). reset t he ad5123 / ad5143 can be reset through software by executing command 14 (see table 15 ). the reset command loads the rdac register s with the contents of the eeprom and takes approximately 30 s. the eeprom is preloaded to midscale at the factory, and in itial power - up is, accordingly, at midscale. shutdown mode the ad5123 / ad5143 can be placed in shutdown mode by executing the software shu tdown command, command 15 (see table 15 ), and setting the lsb (d0) to 1. this feature places the rdac in a zero power consumption state where the device operates in potentiometer mode , terminal a is open - circuited , and the wiper, te rm in a l w , is connected to terminal b; however , a finite wi per resistance of 40 is present. when the device is configured in linear gain setting mode , the resistor addressed, r aw or r wb , is internally place at high impedance . table 14 shows the truth table depending o n the device operat ing mode. the contents of the rdac register are unchanged by entering shutdown mode. however, all commands listed in table 15 are supported while in shutdown mode. execute command 15 (see table 15 ) and se t the lsb (d0) to 0 to exit shutdown mode. table 14 . truth table for shutdown mode linear gain setting m ode potentiometer mode r aw r wb r aw r wb high impedance high impedance high impedance r bs eeprom or rdac register protection th e eeprom and rdac registers can be protected by disabling any update to th e se registers . this can be done by using software or by using hardware. if the se registers are protect ed by software, set bit d0 and/or bit d1 ( see table 17 ) , which protect s the rdac and eeprom registers independently . when rdac is protected, the only operation allowed is to copy the eeprom into the rdac register .
data sheet ad5123/ad5143 rev. a | page 23 of 28 table 15 . advance command s operation truth t able command number co ntrol bits [db15:db12] address bits [db11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing 1 0 0 0 1 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write c ontents of serial register data to rdac 2 0 0 1 0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 x a2 a1 a0 x x x x x x d1 d0 read back contents d1 d0 d ata 0 0 i nput register 0 1 eeprom 1 0 control register 1 1 rdac 4 0 1 0 0 a3 a2 a1 a0 x x x x x x x 1 linear rdac increment 5 0 1 0 0 a3 a2 a1 a0 x x x x x x x 0 linear rdac decrement 6 0 1 0 1 a3 a2 a1 a0 x x x x x x x 1 + 6 db rdac increment 7 0 1 0 1 a3 a2 a1 a0 x x x x x x x 0 ? 6 db rdac decrement 8 0 1 1 0 a3 a2 a1 a0 x x x x x x x x copy input register to rdac (software l r dac) 9 0 1 1 1 0 0 a1 a0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 0 0 a1 a0 x x x x x x x 0 copy eeprom into rdac 11 1 0 0 0 0 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to eeprom 12 1 0 0 1 a3 a2 a1 a0 1 x x x x x x d0 top s cale d0 = 0; normal mode d0 = 1; shutdown mode 13 1 0 0 1 a3 a2 a1 a0 0 x x x x x x d0 bottom s cale d0 = 1; e nter d0 = 0; e xit 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 a3 a2 a1 a0 x x x x x x x d0 software shutdown d0 = 0; normal mode d0 = 1; device placed in sh u tdown mode 16 1 1 0 1 x x x x x x x x d3 d2 d1 d0 copy serial register data to control register 1 x = dont care. table 16 . address bits a3 a2 a1 a0 potentiometer mode linear gain setting mode stored rdac memory input regi ster rdac register input register rdac register 1 x 1 x 1 x 1 all channels all channels all channels all channels not applicable 0 0 0 0 rdac1 rdac1 r wb1 r wb1 rdac1 0 1 0 0 not applicable not applicable r aw1 r aw1 not applicable 0 0 0 1 rdac2 rdac2 r wb2 r wb2 rdac2 0 1 0 1 not applicable not applicable r aw2 r aw2 not applicable 0 0 1 0 rdac3 rdac3 r wb3 r wb3 rdac3 0 1 1 0 not applicable not applicable r aw3 r aw3 not applicable 0 0 1 1 rdac4 rdac4 r wb4 r wb4 rdac4 0 1 1 1 not applicable not applicable r aw4 r aw4 not applicable 1 x = dont care.
ad5123/ad5143 data sheet rev. a | page 24 of 28 table 17 . control register bit description s bit name description d0 rdac register write protect 0 = wiper position frozen to value in eeprom memory 1 = allow s update of wiper position th rough digital interface (default) d1 eeprom program enable 0 = eeprom program disabled 1 = enable s device for eeprom program (default) d2 linear setting mode / potentiometer mode 0 = potentiometer mode (default) 1 = linea r gain setting mode d3 bu rst m ode 0 = d isable d (default) 1 = enable d ( n o disable after stop or repeat start condition)
data sheet ad5123/ad5143 rev. a | page 25 of 28 rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5123/ ad5143 employ a three-stage segmentation approach, as shown in figure 36. the ad5123/ ad5143 wiper switch is designed with the transmission gate cmos topology and with the gate voltage derived from v dd and v ss . 7-bit/8-bit address decoder r l w r l a r h r h r m r m b r m r m r h r h s ts s bs 10878-036 figure 36. ad5123 / ad5143 simplified rdac circuit top scale/bottom scale architecture in addition, the ad5123/ ad5143 include new positions to reduce the resistance between terminals. these positions are called bottom scale and top scale. at bottom scale, the typical wiper resistance decreases from 130 to 60 (r ab = 100 k). at top scale, the resistance between terminal a and terminal w is decreased by 1 lsb, and the total resistance is reduced to 60 (r ab = 100 k). programming the variable resistor rheostat operation8% resistor tolerance the ad5123 / ad5143 operate in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be floating, or it can be tied to terminal w, as shown in figure 37. a w b a w b a w b 10878-037 figure 37. rheostat mode configuration the nominal resistance between terminal a and terminal b, r ab , is 10 k or 100 k, and has 128/256 tap points accessed by the wiper terminal. the 7-bit/8-bit data in the rdac latch is decoded to select one of the 128/256 possible wiper settings. the general equations for determin ing the digitally programmed output resistance between terminal w and terminal b are ad5123: w ab wb rr d dr ??? 128 )( from 0x00 to 0x7f (1) ad5143: w ab wb rr d dr ??? 256 )( from 0x00 to 0xff (2) where: d is the decimal equivalent of the binary code in the 7-bit/8-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance . in potentiometer mode, similar to the mechanical potentiometer, the resistance between terminal w and terminal a also produces a digitally controlled complementary resistance, r wa . r wa also gives a maximum of 8% absolute. r wa starts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equati ons for this operation are ad5123: w ab aw rr d dr ?? ? ? 128 128 )( from 0x00 to 0x7f (3) ad5143: w ab aw rr d dr ?? ? ? 256 256 )( from 0x00 to 0xff (4) where: d is the decimal equivalent of the binary code in the 7-bit/8-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance . if the part is configured in linear gain setting mode, the resistance between terminal w and terminal a is directly proportional to the code loaded in the associate rdac register. the general equations for this operation are ad5123: w ab aw rr d dr ??? 128 )( from 0x00 to 0x7f (5) ad5143: w ab aw rr d dr ??? 256 )( from 0x00 to 0xff (6) where: d is the decimal equivalent of the binary code in the 7-bit/8-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance .
ad5123/ad5143 data sheet rev. a | page 26 of 28 in the bottom scale condition or top scale condition, a finite total wiper resistance of 40 is present. regardless of which setting the part is operating in, limit the current between terminal a to terminal b, terminal w to terminal a, and terminal w to terminal b, to the maximum continuous current of 6 ma or to the pulse current specified in table 5. otherwise, degradation or possible destruction of the internal switch contact can occur. programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper-to-b and wiper-to-a that is proportional to the input voltage at a to b, as shown in figure 38. w a b v a v out v b 10878-038 figure 38. potentiometer mode configuration connecting terminal a to 5 v and terminal b to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 5 v. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is b ab aw a ab wb w v r dr v r dr dv ???? )( )( )( (7) where: r wb (d) can be obtained from equation 1 and equation 2. r aw (d) can be obtained from eq uation 3 and equation 4. operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r aw and r wb , and not the absolute values. therefore, the temperature drift reduces to 5 ppm/c. terminal voltage operating range the ad5123 / ad5143 are designed with internal esd diodes for protection. these diodes al so set the voltage boundary of the terminal operating voltages. positive signals present on terminal a, terminal b, or terminal w that exceed v dd are clamped by the forward-biased diode. there is no polarity constraint between v a , v w , and v b , but they cannot be higher than v dd or lower than v ss . v dd a w b v ss 10878-039 figure 39. maximum terminal voltages set by v dd and v ss power-up sequence because there are diodes to limit the voltage compliance at terminal a, terminal b, and terminal w (see figure 39), it is important to power up v dd first before applying any voltage to terminal a, terminal b, and terminal w. otherwise, the diode is forward-biased such that v dd is powered unintentionally. the ideal power-up sequence is v ss , v dd , digital inputs, and v a , v b , and v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v ss and v dd . regardless of the power-up sequence and the ramp rates of the power supplies, once v dd is powered, the power-on preset activates, which restores eeprom values to the rdac registers. layout and power supply biasing it is always a good practice to use a compact, minimum lead length layout design. ensure that the leads to the input are as direct as possible with a mini mum conductor length. ground paths should have low resistance and low inductance. it is also good practice to bypass the power supplies with quality capacitors. apply low equivalent series re sistance (esr) 1 f to 10 f tantalum or electrolytic capacito rs at the supplies to minimize any transient disturbance and to filter low frequency ripple. figure 40 illustrates the basic supply bypassing configuration for the ad5123 / ad5143. v ss v dd + v dd c1 0.1f c3 10f + c2 0.1f c4 10f v ss ad5123/ ad5143 gnd 10878-040 figure 40. power supply bypassing
data sheet ad5123/ad5143 rev. a | page 27 of 28 outline dimensions 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indi c ator for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 41. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-22) dimensions shown in millimeters ordering guide model 1, 2 r ab (k) resolution interface temperature range package description package option branding ad5123bcpz10-rl7 10 128 i 2 c ?40c to +125c 16-lead lfcsp_wq cp-16-22 dgz ad5123bcpz100-rl7 100 128 i 2 c ?40c to +125c 16-lead lfcsp_wq cp-16-22 dh0 ad5143bcpz10-rl7 10 256 i 2 c ?40c to +125c 16-lead lfcsp_wq cp-16-22 dh1 ad5143bcpz100-rl7 100 256 i 2 c ?40c to +125c 16-lead lfcsp_wq cp-16-22 dh2 EVAL-AD5143DBZ evaluation board 1 z = rohs compliant part. 2 the evaluation board is shipped with the 10 k r ab resistor option; however, the board is compatible with all of the available resistor value options.
ad5123/ad5143 data sheet rev. a | page 28 of 28 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2012C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10878-0-3/13(a)

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